In every level of electronics from smart watches to the cloud, performance efficiency is critical. For the past fifty years, Moore’s law has been the driving force in technology – the ability to double the number of transistors in the same area every two years. Moore’s law in combination with the concepts of Dennard Scaling, the concept that power density in transistors remains constant, has enabled the ability to do the same computing in less space power and cost or more performance in the same space, power, and cost. However, limitations in the traditional characteristics of Moore’s law and Dennard Scaling combined with changes in the dynamics of semiconductor design and manufacturing are putting an emphasis on optimizing the hardware for the workload, which increasingly means selecting or even creating the right processing element for the task . Gone are the days of the big stick – using the latest, fastest, and biggest processor to do everything. Customization at the silicon, packaging, and even the instruction set level is now required to ensure performance efficiency, but each path comes with tradeoffs.
One area of customization that has become most evident in demonstrating this is in the use of specialized functional hardware blocks for critical chip functions such as I/O, power management, security, on-chip networking, and even the workload processing itself. Because of this specialization, most processors are now bundled with additional hardware functions, collectively referred to as a System-on-Chip (SoC). But even within those hardware functions, the flexibility of the core processing architecture, often referred to as the CPU, is critical to maximize performance efficiency, as well as scalability and reusability. One effective way of accomplishing this goal is through custom instructions. Configurable microprocessor architectures that support this level of customization include the Synopsys ARC, RISC-V and Cadence Tensilica processors.
Often lumped in with the Arm architecture as “processor cores,” configurable processor cores offer customization options not available with the Arm architecture. Arm processor IP cores provide the same instruction set to everyone, which confers software compatibility between SoC designs but does not provide the ability to add custom instructions that increase the execution and performance efficiency for specific functions or algorithms. Arm architectural licenses that allow for this level of customization are available, but these licenses are typically limited to high-performance applications like servers where the volume and margins can justify the investment. Architectural licenses also require additional expertise from the customer because Arm has not designed its processors to be customized and does not provide the specialized tools needed to implement the customization.
Synopsys ARC, RISC-V and Cadence Tensilica processors were designed to support custom instructions from the ground up, which means it’s practical to tailor these cores for SoCs designed for even embedded/IoT applications that may be performing very limited tasks. Optimizing even those tasks can improve performance and/or lower power consumption. Customization requires software tools for mapping the code to the custom instructions. Because of the open structure of RISC-V International, tools are contributed by the community, including universities and other developers. However, the RISC-V ISA and tools are relatively new. On the other hand, the Synopsys ARC architecture has been available for 27 years and has been widely used as a power-efficient processing solution in billions of common consumer and embedded applications, such as all the early wi-fi interfaces in the first Intel Centrino mobile PC platforms.
The ARC architecture is a family of IP processors, many optimized for specific types of applications, such as low-power, safety-critical, high-security, high-throughput, high-performance applications, and even AI inference processing. All of these applications benefit from customized instructions. In addition, because it’s under the Synopsys intellectual property (IP) umbrella, the Synopsys ARC architecture is supported by some of the industry’s most advanced software programming tools and complimentary IP.
One of the challenges in designing a new chip or electronics platform is balancing innovation with risk. Innovation in the form of complete customization can offer performance advantages and differentiation at the risk of reducing the reusability of IP, limiting the performance scalability of the design, and increasing the time-to-market and costs of new products. On the other hand, reducing risk through complete standardization can limit differentiation, and most importantly limit performance efficiency.
It is important to select the right processing element for the workload and to selectively use customization where it offers the most benefit. As a result, SoCs in many applications increasingly use a mixture of processing architectures within a single SoC and even for chiplets used in multi-chip modules (MCMs)/system-in-packages (SiPs) designed around specific workload requirements.